[ENGN3213 Home]
- 5206
- Microcomputer Organisation and SBC
- chip
- 5206 Chip
- 68000
- Microcomputer Organisation and SBC
- chip
- 68000 Chip
- active pull-up
- TTL
- address decoding
- Address Decoding
- addressing mode
- Addressing Modes
- ALU
- Other
- AND
- Boolean Functions
- architecture declaration
- VHDL
| Structure of a VHDL
- assembler
- Instruction Sets and Programming
- assembler directives
- Assembly Example
- assembly language
- Instruction Sets and Programming
| Assembly Example
- asserted
- Asserted Levels
- assignment operator
- VHDL
- asynchronous
- What is a Sequential
| Latches and Flip Flops
- inputs
- Asynchronous Inputs
- asynchronous inputs
- Practical Aspects of Sequential
- BCD
- Karnaugh Maps (K-Maps)
- behavioral VHDL
- VHDL
| Structural and Behavioral Examples
- binary coding
- Example - Up/Down/Stop Counter
| Example - Vending Machine
- bistate
- Asserted Levels
- bit manipulations
- Bit Manipulation
- block diagram
- Diagrams
- Boolean algebra
- Boolean Algebra
- boolean variables
- Boolean Variables
- bus
- Tri-state Gates
| Microcomputer Organisation and SBC
| Bus Sizing
| Memory Devices, Buses, Bus
- cycle
- 68000 Bus Timing
- interface
- Bus Interfaces
- timing
- 68000 Bus Timing
- byte
- Bus Sizing
- C
- C Programming
- canonical
- Canonical Forms
- canonical implementation
- Canonical Implementation
- canonical SOP representation
- Canonical Forms
- CCR
- CCR
- clock
- Flip Flops
- clocked
- Latches and Flip Flops
- CMOS
- Digital Gates and Logic
| CMOS
- code converter
- Other
- combinational circuit
- Flip Flops and Related
- combinational logic
- Boolean Functions and Digital
- comparator
- Other
- concurrent statements VHDL
- Processes; Sequential and Concurrent
- constants VHDL
- Signals, Variables and Constants
- control points
- Data Subsystem
- control subsystem
- RTL Systems
| Control Subsystem
- counter
- Counters
| Counters
- D flip flop
- The D Flip Flop
| Types of Latches and
- data movement
- Data Movement
- data subsystem
- RTL Systems
| Data Subsystem
- data types VHDL
- Data Types
- dataflow VHDL
- VHDL
- debouncing
- Switch Debouncing
- decoder
- Decoders and Encoders
- demultiplexer
- Multiplexers and Demultiplexers
- design
- state machine
- Synthesis of Sequential Machines
| Design Steps
- don't cares
- Karnaugh Maps (K-Maps)
- edge triggered
- Latches and Flip Flops
| The D Flip Flop
- encoder
- Decoders and Encoders
- priority
- Decoders and Encoders
- entity declaration
- VHDL
| Structure of a VHDL
- EQV
- Boolean Functions
- exception
- Interrupts and Exceptions
- vector table
- Interrupts and Exceptions
- exclusive NOR
- Boolean Functions
- exclusive OR
- Boolean Functions
- execution graph
- Execution Graphs
- expressions VHDL
- Expressions, Flow Control
- fan out
- Fan Out
- finite state machine
- What is a Sequential
- flip flop
- Flip Flops
| Latches and Flip Flops
| Types of Latches and
- D
- The D Flip Flop
- flow control VHDL
- Expressions, Flow Control
- gated D latch
- The Gated D Latch
- glitch
- Hazards
- race
- Example - Pedestrian Crossing
- how to avoid
- Example - Pedestrian Crossing
- go-no go
- Asynchronous Inputs
- Gray code
- Karnaugh Maps (K-Maps)
- hazard
- Hazards
- cover
- Hazards
- dynamic
- Hazards
- static
- Hazards
- hexadecimal
- Notation
- hold time
- Timing and Metastability
- i/o
- I/O Programming
| I/O Interfaces, Modules, and
- text
- Text
- IAQK cycle
- Interrupts and Exceptions
- IEEE 1164 library
- IEEE 1164 Library
- implementation
- Simplification and Implementation of
- direct
- Direct Implementation
- initialization
- Initialisation and Reset
- instruction set
- Instruction Sets and Programming
- integer arithmetic
- Integer Arithmetic
- interrupt
- Interrupts and Exceptions
- autovectored
- Interrupts and Exceptions
- prioritized
- Interrupts and Exceptions
- service routine
- Interrupts and Exceptions
- vector
- Interrupts and Exceptions
- inverter
- Digital Gates and Logic
| Boolean Functions
- JK flip flop
- Types of Latches and
- K-map
- Karnaugh Maps (K-Maps)
- entered variable
- Entered-Variable K-Maps
- latch
- Flip Flops
| Latches and Flip Flops
| Types of Latches and
- gated D
- The Gated D Latch
- SR
- The SR Latch
- NAND
- The SR Latch
- NOR
- The SR Latch
- level triggered
- Latches and Flip Flops
- local variable
- Local Variables and Stack
- local variables
- C
- Local Variables and Stack
- logic gate
- Digital Gates and Logic
- logical adjacencies
- Karnaugh Maps (K-Maps)
- logical operations
- Logical Operations
- long word
- Bus Sizing
- master-slave D flip flop
- The D Flip Flop
- Mealey machine
- Formal Definition of Finite
- memory map
- Microcomputer Organisation and SBC
| Microcomputer Organisation and SBC
- metastable state
- Timing and Metastability
- microcomputer
- Microcomputer Organisation and SBC
- microinstruction
- Microprogrammed Controller
- format
- Microprogrammed Controller
- microprogram
- Microprogrammed Controller
- microprogrammed controller
- Microprogrammed Controller
- minimal
- Direct Implementation
- minterm
- Decoders and Encoders
- minterm code
- Canonical Forms
- minterms
- Canonical Forms
- mixed logic
- Digital Gates and Logic
| Universality of NAND and
- mixed rail
- The SR Latch
- Moore machine
- Formal Definition of Finite
- multiple-emitter transistor
- TTL
- multiplexer
- Multiplexers and Demultiplexers
- NAND
- TTL
| Boolean Functions
- negative logic
- Digital Gates and Logic
- next state/output table
- Next State/Output Table
- NMOS
- CMOS
- noise margin
- Noise Margin
- NOR
- Boolean Functions
- NOT
- Boolean Functions
- one hot
- Example - Vending Machine
- open-collector
- Open-Collector
- OR
- Boolean Functions
- parallel port
- Parallel Port
- parameter passing
- Parameter Passing
- parity
- Boolean Functions
- physical truth table
- TTL
- PLD
- Direct Implementation
- PMOS
- CMOS
- pointer
- Pointers
- polling
- Polling
- POS
- Canonical Forms
- position independent code
- Position Independent Code
- positive logic
- Digital Gates and Logic
- process VHDL
- Processes; Sequential and Concurrent
| Sequential Machines in VHDL
- product terms
- Canonical Forms
- program control
- Program Control
- program counter
- Programmer's Model
- programmable logic devices
- Programmable Logic Devices
- propagation delay
- Propagation Delays
| Timing and Metastability
- pull-up resistor
- Open-Collector
- race
- Race Conditions
- glitch
- Example - Pedestrian Crossing
- RAM
- RAM
- register
- Registers
| Programmer's Model
- shift
- Registers
- register file
- Register Files
- register transfer level
- Register-Transfer Logic (RTL) Systems
- reset
- Initialisation and Reset
- ROM
- ROM
- flash
- ROM
- RTL
- Register-Transfer Logic (RTL) Systems
- sampling period
- Timing and Metastability
- sanity circuit
- Initialisation and Reset
- sensitivity list VHDL
- Processes; Sequential and Concurrent
- sequential circuit
- Flip Flops and Related
- sequential machine
- What is a Sequential
| What is a Sequential
- serial port
- Serial Port
- set up time
- Timing and Metastability
- shift operations
- Shift Operations
- signal assignment statement
- VHDL
- signal VHDL
- Signals, Variables and Constants
- SOP
- Canonical Forms
- speed-power product
- Speed-Power Product
- SR latch
- The SR Latch
| Types of Latches and
- stack
- Stacks
- stack frame
- Local Variables and Stack
- C
- Local Variables and Stack
- stack pointer
- Programmer's Model
| Stacks
- state
- Formal Definition of Finite
| State Diagram
- redundant
- Equivalence and Redundancy
- state code assignment
- Practical Aspects of Sequential
- state diagram
- Diagrams
| State Diagram
- state machine
- What is a Sequential
| What is a Sequential
- definition
- Formal Definition of Finite
- design
- Synthesis of Sequential Machines
- practical aspects
- Practical Aspects of Sequential
- equivalence
- Equivalence and Redundancy
- VHDL code
- Sequential Machines in VHDL
- state transition
- State Diagram
- static hazard
- Example - Pedestrian Crossing
- status register
- Programmer's Model
- std logic
- Data Types
| IEEE 1164 Library
- structural VHDL
- Structural and Behavioral Examples
- strucural VHDL
- VHDL
- subroutines
- Subroutines
- supervisor mode
- Programmer's Model
- synchronous
- What is a Sequential
| Latches and Flip Flops
- synthesis
- Sequential Machines in VHDL
| Synthesis of Sequential Machines
- T flip flop
- Types of Latches and
- timer
- Timer
- timing
- Timing and Metastability
- timing diagram
- Diagrams
| Timing Diagrams
- totem-pole
- TTL
- tri-state
- Tri-state Gates
- driver
- Bus Interfaces
- triggering
- Latches and Flip Flops
| Triggering
- truth table
- logical
- Boolean Functions
- TTL
- Digital Gates and Logic
| TTL
- UART
- Serial Port
- unclocked
- Latches and Flip Flops
- user mode
- Programmer's Model
- variable VHDL
- Signals, Variables and Constants
- VHDL
- VHDL
- behavioral
- VHDL
- dataflow
- VHDL
- state machine code
- Sequential Machines in VHDL
- strucural
- VHDL
- wired-AND
- Open-Collector
- word
- Bus Sizing
- XOR
- Boolean Functions
[ENGN3213 Home]
ANU Engineering - ENGN3213