The Gated D Latch

We now use an SR latch to build a gated D latch, Figure 59.

**Figure 59:** Gated D latch.
$\begin{figure} \begin{center} \epsfig{file=images/seqimg8.eps}\end{center}\end{figure}$

The operation of this latch is described by the following table:

So when the device is disabled (E=0), it holds its current value, and when enabled (E=1), it can be set or reset. I.e. E=1 implies Q=D.

A circuit implementation of the gated D latch is shown in Figure 60.

**Figure 60:** Gated D latch circuit.
$\begin{figure} \begin{center} \epsfig{file=images/seqimg9.eps}\end{center}\end{figure}$

This is described by the equations

$\begin{displaymath}\begin{array}{rl} S & = DE \\ R & = \overline{D} E \end{array}\end{displaymath}$

A waveform illustrating the operation of the gated D latch is shown in Figure 61.

**Figure 61:** Gated D latch waveform.
$\begin{figure} \begin{center} \epsfig{file=images/seqimg10.eps}\end{center}\end{figure}$

Note that Q responds to changes in D while E is active - this is called transparency.

By connecting E to a clock signal, this device could be used as a level triggered flip flop.

However, level trigger FFs are not often used because of transparency and other problems.

ANU Engineering - ENGN3213