We want a FF that responds to a clock edge, either rising or falling. One design is the master-slave type, Figure 62.
This circuit is designed to respond to the falling edge, Figure 63 (propagation delays shown).
The standard circuit symbols for the rising and falling edge triggered D flip flops are shown in Figure 64.
Reading: Wakerly, Sections 7.1 and 7.2 (pp531).
ANU Engineering - ENGN3213