Timing and Metastability

Timing is a very important issue in state machine design. In order for a carefully sequenced design to work correctly, various timing conditions must be met. See Figure 65.

**Figure 65:** Timing parameters.
$\begin{figure} \begin{center} \epsfig{file=images/seqimg14.eps}\end{center}\end{figure}$

t_su - set up time: the minimum time period immediately prior to an active clock edge during which the input data must remain stable.
t_h - hold time: the minimum time period immediately after an active clock edge during which the input data must remain stable.
t_w - pulse width: width of the clock pulse.
t_p - propagation delay: time taken for the output to stabilize after each active clock edge.
The sampling interval is the sum t_su+t_h, and data should be stable for this time period.

Flip flop data sheets specify the values for these (and other) parameters which the designer must take into account. For instance, set up and hold times must be met when applying data to a flip flop.

If the setup and hold time requirements are not met, then correct operation of the memory element and hence of the state machine cannot be guaranteed.

For instance, suppose t_su = 20 ns, be the data arrives only 10 ns before the active clock edge. Then the device can enter a metastable state, Figure 66.

**Figure 66:** Metastable behaviour.
$\begin{figure} \begin{center} \epsfig{file=images/seqimg15.eps}\end{center}\end{figure}$

The late arriving data can push Q half-way from LOW to HIGH, i.e. somewhere in the invalid range of voltages. This can cause problems and errors in circuits connected to Q.

Moreover, Q can go either LOW or HIGH, so the next state is unpredictable.

Metastable states should be avoided.

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