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Structural and Behavioral Examples

We saw earlier a dataflow description of the combinational circuit of Figure 48. Here is a behavioral description:  

library IEEE;
use IEEE.std_logic_1164.all;

entity comb_cct is
    port (
        A: in STD_LOGIC;
        B: in STD_LOGIC;
        C: in STD_LOGIC;
        X: out STD_LOGIC
    );
end comb_cct;

architecture comb_cct_behav_arch of comb_cct is
begin
    process(A,B,C)
    variable TEMP : STD_LOGIC;
    begin
         TEMP := A and B;
         X <= TEMP or C;
    end process;
end comb_cct_behav_arch;

And here is a structural description:  

library IEEE;
use IEEE.std_logic_1164.all;

entity comb_cct is
    port (
        A: in STD_LOGIC;
        B: in STD_LOGIC;
        C: in STD_LOGIC;
        X: out STD_LOGIC
    );
end comb_cct;

architecture comb_cct_struct_arch of comb_cct is
component and_gate
     port(x, y : in std_logic; 
          z    : out std_logic);
end component;
component or_gate
     port(x, y : in std_logic; 
          z    : out std_logic);
end component;
signal w : std_logic;
begin
     and_gate1 : and_gate port map (A,B,w);
     or_gate1  : or_gate  port map (w,C,Z);
end comb_cct_struct_arch;

library IEEE;
use IEEE.std_logic_1164.all;

entity and_gate is
     port(x, y : in std_logic; 
          z    : out std_logic);
end and_gate;

architecture and_gate_arch of and_gate is
begin
     z <= x and y;
end and_gate_arch;

library IEEE;
use IEEE.std_logic_1164.all;

entity or_gate is
     port(x, y : in std_logic; 
          z    : out std_logic);
end or_gate;

architecture or_gate_arch of or_gate is
begin
     z <= x or y;
end or_gate_arch;

Of course, the and $\underline\$gate and or $\underline\$gate components would could be defined somewhere else (such as in a library or another file).

Note that this structural description closely matches the schematic diagram in Figure 48.