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68000 Bus Timing

  As computers spend a lot of their time transferring data to and from memory, it is important to have some appreciation of the processes involved and their timing. Chapter 4 of Clements devotes considerable attention to this; here we look briefly at a few points.

The basic read cycle for the 68000 is as follows (abbreviated), Figure 129:

CPU	Memory
Set $R/\overline{W}$ to read
Place address on A01-A23
Assert address strobe AS
Assert UDS and LDS
	Decode address
	Place data on D00-D15
	Assert DTACK
Latch data
Negate UDS and LDS
Negate AS
	Remove data from D00-D15
	Negate DTACK

This is an asynchronous read cycle, and uses interlocked handshacking via the signals AS (indicates address valid) and DTACK (indicates data valid). The data strobe signals UDS and LDS specify the size of the data being transferred via the 16 bit data bus (the 5206 uses its SIZ pins with its 32 bit data bus).

  

Figure 129: CPU-memory interface.

  The asynchronous read bus cycle consists of a minimum of four clock cycles, consisting of eight states S0-S7. Additional wait states may be inserted to accommodate slow memory devices. Figure 130 shows the basic read timing diagram.

  

Figure 130: Read cycle timing diagram.

Here, the address becomes valid in S1, which is indicated to the memory by asserting AS in state S2, at which time the data strobe is asserted. The memory acknowledges this in state S4 and asserts DTACK, informing the CPU that data will be placed on the data bus, which occurs later in state S6. If DTACK is late in being asserted during state S4, additional wait states are introduced between states S4 and S5 until DTACK is asserted.

Detailed documentation is provided in Section 5 of the Motorola M68000 User Manual, and in Section 6 of the Motorola MCF5206 User Manual.

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