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Bus Interfaces

  Figure 121 shows a simple bus arrangement with several devices attached.

  

Figure 121: Bus interface.

Physically the bus consists of one or more wires, and each device makes connections to one or more of these wires. Recall, e.g., that the data bus of the 5206 is 32 bits wide.

It is very important to understand that only one device can place data on the bus at any one time. A piece of wire cannot be forced HIGH by one device, and LOW by another at the same time! However, any number of devices can read from the bus (subject to electrical limitations).

Consequently, buses must be controlled so that at most one device can place data at any given time. Many devices have tri-state gates or drivers to facilitate bus control.  

Figure 122 shows the circuit symbol for a 3-state driver.

  

Figure 122: Tri-state driver.

The operation of the tri-state driver is summarised in the table:

Enable	Input	Output
L	X	Hi-Z
H	L	L
H	H	H

When E is H, the gate is enabled and behaves like a normal buffer, so that X=A; when E is L, the gate output is disabled, and there is a high impedance looking into the output (the ouput is essentially open-circuited).

Figure 123 shows two devices connected to a bus, together with a simple bus control circuit. When SEL=0, device 0 is connected to the bus and can place data on the bus, while device 1 is disconnected. When SEL=1, device 1 is connected to the bus and can place data on the bus, while device 0 is disconnected. In this example, it is assumed that any other devices (not shown) connected to the bus only read data from it.

  

Figure 123: Tri-state drivers and bus control.

Some devices have pins that can be configured for either input or output. These devices use a pair of 3-state drivers to control the connection. Examples include the Xilinx FPGA I/O pins and the Motorola 5206 parallel port pins.

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