TTL

Historically the TTL series has been very important and widely used, but is now being taken over by CMOS. TTL is high speed, low power, and economical.

A standard TTL NAND gate is shown in Figure 3, with transfer characteristic shown in Figure 4.

**Figure 3:** TTL NAND gate.
$\begin{figure} \begin{center} \epsfig{file=images/digdevimg3.eps}\end{center}\end{figure}$

**Figure 4:** TTL NAND gate characteristics (V_B=0).
$\begin{figure} \begin{center} \epsfig{file=images/digdevimg4.eps}\end{center}\end{figure}$

Acceptable values for L might be 0-0.8 V, and for H, say 2.0-5.0 V. Detailed information on the voltage values can be found in the TTL data sheets. Propagation delay for 74LS devices is 9.5 ns, and fan-out is 20. Noise margin is of the order 400 mV.

In Figure 3, the transistor Q₁ is called a multiple-emitter transistor. The transistors Q₃ and Q₄ form an output arrangement called totem-pole. Transistor Q₃ provides an active pull-up output (instead of a passive resistor), which is fast.

If A or B is L, then Q₁ and Q₃ are on, and Q₂ and Q₄ are off, so that Y is H. In fact Y will be around 3.4-3.8 V. If a load is connected to Y, increased current will be drawn through resistor R₃ causing the collector voltage of Q₃ to fall, and if the load current is too great (say caused by a number of load gates greater than the fan-out) then the logic level at Y may be invalid. A substantial current I_IL of the order 1.1 mA will flow out of the input A, and so the input source acts as a sink to ground for this current.

If both A and B are H, then Q₁ and Q₃ are off, and Q₂ and Q₄ are on, so Y is L, around 0.2 V. With Q₃ off, the main source off current through Q₄ is from the output Y (which is typically connected to other TTL inputs). The output impedance when Q₄ is on is low, typically 10 $\Omega$ . Only a small current I_IH of the order 10 $\mu$ A needs to be supplied from the input source.

The truth table which summarises the behaviour of this NAND gate is

INPUT		OUTPUT
L	L	H
L	H	H
H	L	H
H	H	L

This is called the physical truth table. Of course, with positive logic this gives the usual logical NAND function. However, using mixed logic it is possible to interpret this physical gate as and AND, OR or NOR logic gates, which have compleletly different logical truth tables. For instance, to obtain the logical AND operation from the physical NAND gate, we use positive logic at the inputs, but negative logic at the output. See Section 2.7.

Other types of physical gates are availables, such as NOR, etc.

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