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Address Decoding

  Address decoding refers to the way a computer system decodes the addresses on the address bus to select memory locations in one or more memory or peripheral devices. The 68000's 23-bit address bus permits 2²³ 16-bit words to be uniquely addressed.

In full address decoding, each addressable memory location corresponds to a unique address value on the address bus. Figure 126 shows an example of two memory devices configured using full address decoding. Memory M1 is selected whenever A₁₂- A₂₃=000000000000, while M2 is selected whenever A₁₂- A₂₃=100000000000.

  

Figure 126: Full address decoding of two memory devices.

In partial address decoding, not all address lines in the address bus are used in the decoding process. Figure 127 shows two memory devices configured using partial decoding, where A₂₃ is used to distinguish between the two. In this example, M1 and M2 are repeated 2,048 times through the memory space. When A₂₃=0, M1 is selcted; when A₂₃=1, M2 is selected.

  

Figure 127: Partial address decoding of two memory devices.

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