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Example - Pedestrian Crossing Controller

Figure 78 shows a single lane road with a pedestrian crossing. Road traffic and pedestrians are controlled by light signals. Pedestrians may request to cross the road by pressing a walk button W.

  

Figure 78: Pedestrian crossing.

The traffic lights are controlled by a synchronous state machine, with state diagram as shown in Figure 79.

  

Figure 79: Pedestrian crossing traffic light controller.

This is very much idealised. The system should go to the state corresponding to R, HALT on RESET or power up.

The next state/output table for the pedx controller is as follows:

Present state	next state	output
s0	s0 if $\overline{W}$,	G, HALT
	else s1 if W
s1	s2	Y, HALT
s2	s3	R, WALK
s3	s0	R, HALT

Let's do something different and use two falling edge triggered JK flip flops with active low preset and preclear as memory elements. Use AB as a pair of state variables to label the flip flops, with natural binary as our coding (in this example this turns out not to be the best choice, as we will see). We need to work out the next state and output logic, making use of the state transition table for the JK flip flop.

The binary version of the next state/output table is as follows:

Present state	next state	G	Y	R	WALK	HALT
00	00 if W=0,	1	0	0	0	1
	else 01 if W=1
01	10	0	1	0	0	1
10	11	0	0	1	1	0
11	00	0	0	1	0	1

The k-maps for the Boolean functions J_A, K_A, J_B, K_B are shown in Figure 80.

  

Figure 80: Next state k-maps for pedx controller.

This gives:

$$\begin{array}{rl} J_A & = B \\ K_A & = B \\ J_B & = A + W \\ K_B & = 1 \end{array}$$

The k-maps for the output signals are shown in Figure 81.

  

Figure 81: Output k-maps for pedx controller.

This gives:

$$\begin{array}{rl} R & = A \\ Y & = \overline{A}. B \\ G & =... ... + B = \overline{WALK} \\ WALK & = A. \overline{B} \end{array}$$

A circuit diagram of the pedx controller is given in Figure 82.

  

Figure 82: Circuit diagram for the pedx controller.

Some practical issues. Output race glitches may occur in the output signals, e.g. HALT. Consider the transition

$$AB=11 \to AB=00$$

which involves two flip flops changing state simultaneously, a race condition. See Figure 83.

  

Figure 83: K-map for HALT illustrating race condition.

   

Since we can't predict which path the machine will take, we may or may not get a glitch as the figure shows.

Exercise. Examine other outputs for possible glitches (either due to races, or hazards in the output logic).

Question? Will glitches cause problems?

This depends on what the signals are used for.

• There should be no problems with glitches in the next state logic, since the glitch will be over well before the next active clock edge.

• If an outputs signal drives LEDs, e.g., no problems should arise (too fast to see).

• However, if the output signal is an input to further logic, then glitches may pose a potential problem if unwanted actions are initiated.

  How to avoid problems with glitches (if necessary).

• State code assignment. Do this in a way which minimises or avoids races by ensuring at most one flip flop changes (if possible).

  A better choice of code in this example would be the Gray code:

  State	old code	new (Gray) code
  s0	00	00
  s1	01	01
  s2	10	11
  s3	11	10

  Use of this new coding will result in a design free of races, and race glitches.

  Sometimes it might be necesssary to add additional states called fly states to achieve this, Figure 84.

  
  

    

  Figure 84: Fly states.

  
  
  

• Remove any static hazards in the output logic.  

• Filter out the glitch. Figure 85 shows a circuit sometimes ussed to filter out glitches; here a finite state machine (negative edge triggered) has an output HALT with glitches, while HALT' will be glitch-free, but delayed by half a clock cycle.

  
  

    

  Figure 85: Filtering out race glich.

  
  
  

• Be careful with asynchronouus inputs appearing in conditional outputs (these can introduce glitches).

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