Index

Instruction Sets and Programming

address decoding

addressing mode

ALU

AND

architecture declaration

VHDL | Structure of a VHDL

assembler

assembler directives

Assembly Example

assembly language

Instruction Sets and Programming | Assembly Example

asserted

Asserted Levels

assignment operator

Practical Aspects of Sequential

asynchronous

What is a Sequential | Latches and Flip Flops

inputs: Asynchronous Inputs

asynchronous inputs

BCD

Example - Up/Down/Stop Counter | Example - Vending Machine

behavioral VHDL

VHDL | Structural and Behavioral Examples

binary coding

bistate

Asserted Levels

bit manipulations

Bit Manipulation

block diagram

Diagrams

Boolean algebra

Boolean Algebra

boolean variables

Boolean Variables

bus

Tri-state Gates | Microcomputer Organisation and SBC | Bus Sizing | Memory Devices, Buses, Bus

cycle: 68000 Bus Timing
interface: Bus Interfaces
timing: 68000 Bus Timing

byte

Bus Sizing

C

C Programming

canonical

canonical implementation

Canonical Implementation

canonical SOP representation

Boolean Functions and Digital

CCR

CCR

clock

Flip Flops

clocked

Latches and Flip Flops

CMOS

Digital Gates and Logic | CMOS

code converter

Other

combinational circuit

Flip Flops and Related

combinational logic

comparator

Other

concurrent statements VHDL

Processes; Sequential and Concurrent

constants VHDL

Signals, Variables and Constants

control points

Data Subsystem

control subsystem

RTL Systems | Control Subsystem

counter

Counters | Counters

D flip flop

The D Flip Flop | Types of Latches and

data movement

Data Movement

data subsystem

RTL Systems | Data Subsystem

data types VHDL

Data Types

dataflow VHDL

Multiplexers and Demultiplexers

debouncing

Switch Debouncing

decoder

Decoders and Encoders

demultiplexer

design

state machine: Synthesis of Sequential Machines | Design Steps

don't cares

edge triggered

Latches and Flip Flops | The D Flip Flop

encoder

Decoders and Encoders

priority: Decoders and Encoders

entity declaration

VHDL | Structure of a VHDL

EQV

Interrupts and Exceptions

exception

vector table: Interrupts and Exceptions

exclusive NOR

exclusive OR

Expressions, Flow Control

execution graph

Execution Graphs

expressions VHDL

fan out

Fan Out

finite state machine

What is a Sequential

flip flop

Flip Flops | Latches and Flip Flops | Types of Latches and

D: The D Flip Flop

flow control VHDL

Expressions, Flow Control

gated D latch

The Gated D Latch

glitch

Hazards

race

Example - Pedestrian Crossing

how to avoid: Example - Pedestrian Crossing

go-no go

Asynchronous Inputs

Gray code

hazard

Hazards

cover: Hazards
dynamic: Hazards
static: Hazards

hexadecimal

Notation

hold time

Interrupts and Exceptions

i/o

I/O Programming | I/O Interfaces, Modules, and

text: Text

IAQK cycle

IEEE 1164 library

IEEE 1164 Library

implementation

Simplification and Implementation of

direct: Direct Implementation

initialization

Initialisation and Reset

instruction set

Instruction Sets and Programming

integer arithmetic

Integer Arithmetic

interrupt

Interrupts and Exceptions

autovectored: Interrupts and Exceptions
prioritized: Interrupts and Exceptions
service routine: Interrupts and Exceptions
vector: Interrupts and Exceptions

inverter

Digital Gates and Logic | Boolean Functions

JK flip flop

Types of Latches and

K-map

Local Variables and Stack

entered variable: Entered-Variable K-Maps

latch

Flip Flops | Latches and Flip Flops | Types of Latches and

gated D

The Gated D Latch

SR

The SR Latch

NAND: The SR Latch
NOR: The SR Latch

level triggered

Latches and Flip Flops

local variable

local variables

C: Local Variables and Stack

logic gate

Digital Gates and Logic

logical adjacencies

Formal Definition of Finite

logical operations

Logical Operations

long word

Bus Sizing

master-slave D flip flop

The D Flip Flop

Mealey machine

memory map

Microcomputer Organisation and SBC | Microcomputer Organisation and SBC

metastable state

Microcomputer Organisation and SBC

microcomputer

microinstruction

Microprogrammed Controller

format: Microprogrammed Controller

microprogram

Microprogrammed Controller

microprogrammed controller

Microprogrammed Controller

minimal

Direct Implementation

minterm

Decoders and Encoders

minterm code

minterms

Digital Gates and Logic | Universality of NAND and

mixed logic

mixed rail

The SR Latch

Moore machine

Formal Definition of Finite

multiple-emitter transistor

Multiplexers and Demultiplexers

multiplexer

NAND

TTL | Boolean Functions

negative logic

Digital Gates and Logic

next state/output table

Next State/Output Table

NMOS

noise margin

NOR

NOT

one hot

Example - Vending Machine

open-collector

Open-Collector

OR

parallel port

Parallel Port

parameter passing

Parameter Passing

parity

physical truth table

Position Independent Code

PLD

Direct Implementation

PMOS

pointer

polling

POS

position independent code

positive logic

Digital Gates and Logic

process VHDL

Processes; Sequential and Concurrent | Sequential Machines in VHDL

product terms

program control

Program Control

program counter

Programmable Logic Devices

programmable logic devices

propagation delay

Propagation Delays | Timing and Metastability

pull-up resistor

Open-Collector

race

Race Conditions

glitch: Example - Pedestrian Crossing

RAM

RAM

register

Registers | Programmer's Model

shift: Registers

register file

register transfer level

reset

Initialisation and Reset

ROM

ROM

flash: ROM

RTL

sampling period

Processes; Sequential and Concurrent

sanity circuit

Initialisation and Reset

sensitivity list VHDL

sequential circuit

Flip Flops and Related

sequential machine

What is a Sequential | What is a Sequential

serial port

Serial Port

set up time

shift operations

Shift Operations

signal assignment statement

Signals, Variables and Constants

signal VHDL

SOP

Local Variables and Stack

speed-power product

Speed-Power Product

SR latch

The SR Latch | Types of Latches and

stack

Stacks

stack frame

C: Local Variables and Stack

stack pointer

Programmer's Model | Stacks

state

Formal Definition of Finite | State Diagram

redundant: Equivalence and Redundancy

state code assignment

Practical Aspects of Sequential

state diagram

Diagrams | State Diagram

state machine

What is a Sequential | What is a Sequential

definition

Formal Definition of Finite

design

Synthesis of Sequential Machines

practical aspects: Practical Aspects of Sequential

equivalence

Equivalence and Redundancy

VHDL code

Sequential Machines in VHDL

state transition

State Diagram

static hazard

Example - Pedestrian Crossing

status register

Structural and Behavioral Examples

std logic

Data Types | IEEE 1164 Library

structural VHDL

strucural VHDL

subroutines

Subroutines

supervisor mode

Sequential Machines in VHDL | Synthesis of Sequential Machines

synchronous

What is a Sequential | Latches and Flip Flops

synthesis

T flip flop

Types of Latches and

timer

Timer

timing

timing diagram

Diagrams | Timing Diagrams

totem-pole

tri-state

Tri-state Gates

driver: Bus Interfaces

triggering

Latches and Flip Flops | Triggering

truth table

logical: Boolean Functions

TTL

Digital Gates and Logic | TTL

UART

Serial Port

unclocked

Latches and Flip Flops

user mode

Signals, Variables and Constants

variable VHDL

VHDL

behavioral: VHDL
dataflow: VHDL
state machine code: Sequential Machines in VHDL
strucural: VHDL

wired-AND

Open-Collector

word

Bus Sizing

XOR