VHDL

VHDL is a language for expressing electrical hardware designs at various levels, ranging from low level descriptions of component interconnections to high level abstract representations of behavior. VHDL is widely used in industry and is an IEEE Standard. It is a powerful and flexibile language, and in this course we focus on a subset sufficient for basic combinational and sequential digital circuit design.

There are three basic techniques used in VHDL coding, and a VHDL design file can include one or more of these techniques:

1.: Structural. Specifies how components such as gates are interconnected.
2.: Data flow. Specifies how data flows from input signals to output signals.
3.: Behavioral. Specifies in terms of a sequential algorithm how outputs are determined from inputs.

To get a quick feel for VHDL, consider the digital circuit of Figure 47.

**Figure 47:** A digital circuit.
$\begin{figure} \begin{center} \epsfig{file=images/combvhdlimg1.eps}\end{center}\end{figure}$

This circuit represents the Boolean function

X = AB + C

and can be viewed in input-output terms as shown in Figure 48.

**Figure 48:** Digital circuit black box with inputs and outputs.
$\begin{figure} \begin{center} \epsfig{file=images/combvhdlimg2.eps}\end{center}\end{figure}$

In VHDL, this circuit can be represented by a signal assignment statement

X <= (A and B) or C

The symbol <= is the assignment operator. VHDL code for digital systems may consist of a set of statements within an architecture declaration, together with a specification of external interfaces via ports, listing signals that are to be inputs or outputs, in an entity declaration. As we shall see, VHDL is capable of specifying digital circuits at many levels of abstraction; the VHDL code above is behavioral or dataflow. A complete VHDL file for this circuit is as follows:

library IEEE;
use IEEE.std_logic_1164.all;

entity comb_cct is
    port (
        A: in STD_LOGIC;
        B: in STD_LOGIC;
        C: in STD_LOGIC;
        X: out STD_LOGIC
    );
end comb_cct;

architecture comb_cct_arch of comb_cct is
begin
  X <= (A and B) or C;
end comb_cct_arch;

In this VHDL file, note:

The entity and architecture specifications, and how they specify the inputs and outputs, and the combinational logic, respectively.
The signals are declared as STD $\underline\$ LOGIC, a type we will always be using which comes from the IEEE Standard 1164.
This file is a dataflow description of the digital circuit.

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