[ENGN3213 Home]

Latches and Flip Flops

Having gained some familiarity with state machines in general terms, we now spend some time with the building blocks of state machines, viz. memory elements. Memory elements allow digital systems to remember the outcomes of previous events. The Xilinx 4000E FPGA chip contains flip flops in its IOBs and CLBs.

    Specifically, we now look at latches and flip flops.

As we shall see, latches are memory elements without any clock inputs, whereas flip flops are memory elements that respond to a clock input.

There are a number of types of latches/flip flops:

1.

SR (set-reset)

2.

D (data)

3.

T (toggle)

4.

JK

We will learn how to design state machines using these (and other) memory elements.

        Triggering is a key issue; the memory element may be

1.

clocked (synchronous) or unclocked (asynchronous)

2.

      level or edge triggered

We will see what these terms mean in what follows.

[ENGN3213 Home]