International Workshop on OpenMP (IWOMP)

Workshop program

Tuesday, September 17

9:00 - 14:15

Registration / Check-in

9:45

Keynote

The Role of OpenMP in Extreme Scale Software

Vivek Sarkar
E.D. Butcher Chair in Engineering
Rice University

Recent changes in the OpenMP standard (including support for task parallelism, accelerators, SIMD parallelism, thread affinity, task cancellation) have begun addressing some of the anticipated requirements for Extreme Scale systems, but many challenges still remain. In general, a holistic redesign of the entire software stack is needed to address the programmability and performance requirements of Extreme Scale systems. This redesign will need to span programming models, languages, compilers, runtime systems, and system software. In this talk, we focus on the critical role played by the runtime system in enabling programmability in upper layers of the software stack, and in enabling performance in lower levels of hardware.

Click here for a detailed abstract of this presentation

10:45

Break

University House Common Room

11:15

Session 1: Extensions for OpenMP
Chair: Barbara Chapman

A Proposal for Task-Generating Loops in OpenMP

Xavier Teruel, Michael Klemm, Kelvin Li, Xavier Martorell, Stephen Olivier, and Christian Terboven

Using OpenMP under Android

Vikas, Travis Scott, Nasser Giacaman, and Oliver Sinnen

Expressing DOACROSS Loop Dependencies in OpenMP

Jun Shirako, Priya Unnikrishnan, Sanjay Chatterjee, Kelvin Li, and Vivek Sarkar

12:45

Lunch

University House Common Room

13:45

Session 2: Applications
Chair: Josh Milthorpe

Manycore Parallelism through OpenMP: High Performance Scientific Computing with Xeon Phi

James Barker and Josh Bowden

Performance Characteristics of Large SMP Machines

Dirk Schmidl, Dieter an Mey and Matthias S. Müller

Evaluating OpenMP Tasking at Scale for the Computation of Graph Hyperbolicity

Aaron B. Adcock, Blair D. Sullivan, Oscar R. Hernandez, and Michael W. Mahoney

15:15

Break

University House Common Room

15:30

Session 3: Accelerators
Chair: Bronis de Supinski

Early Experiences with the OpenMP Accelerator Model

Chunhua Liao, Yonghong Yan, Bronis R. de Supinski, Daniel J. Quinlan, and Barbara Chapman

An OpenMP Barrier using SIMD Instructions for Intel Xeon Phi Coprocessor

Diego Caballero, Alejandro Duran, and Xavier Martorell

OpenMP on the Low-Power TI Keystone II ARM/DSP System-On-Chip

Eric Stotzer, Ajay Jayaraj, Murtaza Ali, Arnon Friedmann, Gaurav Mitra, Alistair P. Rendell, and Ian Lintault

19:30 - 22:00

Reception / Banquet

Benchmark Wine Bar, 65 Northbourne Ave, Canberra City

Wednesday, September 18

9:00

Keynote

Caches, Critical Sections & Transactional Memory

James Goodman
University of Auckland

Transactional memory is implemented by speculating about potential concurrency, depending on the knowledge of a hierarchical, shared memory system to detect when violations occur. Hardware can similarly be employed to detect actual conflicts when speculatively executing critical sections concurrently, relying on the cache consistency mechanism to guarantee a legal execution. I will review cache memories, the problems they create and solve, and the resulting opportunities they present for exploiting concurrency.

9:30

Keynote

Transactional memory: language features and hardware support

Mark Moir
Oracle Corporation

This talk will give an overview of the latest proposal for adding transactional features to the C++ language, and provide some examples demonstrating the power of transactional programming to simplify concurrent programming and improve scalability.
We will also discuss hardware transactional memory and how it can be exploited by such language features, or more immediately and directly using lock elision.