In general, gate outputs should not be tied together unless the output circuitry is specifically designed to do so. The basic problem is that each gate may have different output states, and these can be in conflict, e.g. gate 1 may be H and gate 2 may be L.
If two TTL totem-pole outputs are joined together, say by a wiring error, and one is H and the other L, then large currents (say 55 mA) can flow. These currents can result in damage and invalid logic levels. The point at which the TTL outputs are tied will be the logical AND of the two outputs (why?). The behaviour of CMOS gates is less predictable.
ANU Engineering - ENGN3213