Description

In this HLAB you are asked to implement and test on the Xilinx FPGA hardware a 4-bit ALU, Figure 45.

**Figure 45:** 4-bit ALU.
$\begin{figure} \begin{center} \epsfig{file=images/alu4.eps}\end{center}\end{figure}$

The table below describes the logical (M=0) and arithmetic (M=1) operations of a simple 1-bit ALU. The block diagram is shown in Figure 45.

M	S	F
0	0	A + B
0	1	$A \oplus B$
1	0	$A \ {\rm plus}\ B$ (full adder)
1	1	$A\ {\rm minus}\ B$ (full subtractor)

**Figure 46:** 1-bit ALU block diagram.
$\begin{figure} \begin{center} \epsfig{file=images/alu.eps}\end{center}\end{figure}$

The 4-bit ALU has 5 inputs M,S,Z_in,A,B and two outputs F,Z_out. In logical mode, F is either A+B or $A \oplus B$ depending on the value of the selection bit S. In arithmetic mode, F, Z_out is either the full adder output or the full subtractor output of A,B,Z_in depending on the value of the selection bit S ( Z_in=C_in or B_in, and Z_out=C_out or B_out).

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