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Xilinx Demo Board

The Xilinx demo board is shown in Figure 67. Note the layout and resources available. Please do not alter the configuration switches.


  
Figure 67: Xilinx Demo Board.
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\epsfig{file=images/xboard0.eps}\end{center}\end{figure}

The Xilinx demo Board has the following resources:

1.
Eight switches, Table 2.

2.
Eight LEDs (active low), Table 3.

3.
Two 7-segment displays, Table 4 and Figure 68.

4.
External conections, Table 5.

5.
Miscellaneous items, including clock connection, Tables 5 and 6.


 
Table 2: Xilinx switch: SW3 (8 mini switches)
SW3-1 P19
SW3-2 P20
SW3-3 P23
SW3-4 P24
SW3-5 P25
SW3-6 P26
SW3-7 P27
SW3-8 P28
 


 
Table 3: Xilinx LED (8 single LEDs, ACTIVE LOW)
d1 P61
d2 P62
d3 P65
d4 P66
d5 P57
d6 P58
d7 P59
d8 P60
 


  
Figure 68: Xilinx Board 7 segement display.
\begin{figure}
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\epsfig{file=images/7seg.eps}\end{center}\end{figure}


 
Table 4: Xilinx 7-Segment LEDs (2 units)
  U7 U8
a P39 P49
b P38 P48
c P36 P47
d P35 P46
e P29 P45
f P40 P50
g P44 P51
d.p. P37 P41
 


 
Table 5: Xilinx external connections.
Function Xilinx pin
Clock P13
Spare P18
IO 0 P10
IO 1 P9
IO 2 P8
IO 3 P7
IO 4 P6
IO 5 P5
IO 6 P4
IO 7 P3
IO 8 P84
IO 9 P83
IO 10 P82
IO 11 P81
IO 12 P80
IO 13 P79
IO 14 P78
IO 15 P77
Prog P55
Reset P56
 


 
Table 6: Xilinx misc.
Osc  (CLOCK) P13  (PGCLK1)
sw1-inp P69
RESET P56
SPARE P18
PROG P55
 

Note 1:
There is a row of pins all connected to ground at the Xilinx end. One of these ground pins must be connected to ground on the trainer board.

Note 2:
cable pins are each connected through a 270 ohm series resistor to limit current to approx. 20mA in the case of a ground to +5V short.

Note 3:
The Xilinx CLOCK (pin P13) must be connected to the TTL clock generator on the trainer board when implementing sequential designs (state machines). Your project .ucf file must specify pin P13 as the clock input.


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