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Programmable Devices

Field Programmable Gate Arrays (FPGAs   are integrated circuit chips which are capable of implementing digital logic (combinational as well as sequential). The devices can be programmed and reprogrammed many times in circuit. FPGAs can replace large numbers of discrete devices. They can be used for reconfigurable computing,   where the device configuration can be changed according to need, so that one chip can perform the function of many. FPGAs and microprocessors/microcontrollers account for the major part of modern digital systems.

For example, the Xilinx XC4003EPG84 chips we use have 238 logic cells, up to 3000 logic gates, and 360 flip flops.

The FPGA devices store programmed configuration data in a volatile RAM-like manner, Figure 63. The XC devices are programmed by loading them with a bit stream of configuration data from either a PROM or from a host computer via a download cable. In some sense the XC devices are like very long configurable shift registers. The XC devices have 3 major elements:

• CLBs (configurable logic blocks)

• IOBs (input output blocks)

• programmable interconnections

  

Figure 63: FPGA layout.

CLB (configurable logic blocks)

Digital designs are spread over an array of CLBs, Figure 64, which are configured to implement the required logical and state machine functionality. XC4000 series devices have 100 CLBs in a 10 x 10 matrix. Each CLB has the following configurable features:

• 2 independent 4-input combinational logic functions (implemented as look-up tables).

• 2 D flip-flops

  

Figure 64: Configurable logic block.

IOB (input - output blocks)

These provide connection between the internal logic and external package pins. XC4000 devices have between 64 and 192 IOBs, Figure 65. Each IOB is configurable and consists of

• 1 external pin, which can serve as
  • input,

  • output, or

  • bidirectional

• registers

• 3-state mode

• testing facilities, etc

  

Figure 65: Input-output block.

Programmable Interconnects

XC devices have internal networks for interconnecting the CLBs and IOBs. The connections are programmed as part of the design implementation. See Figure 66.

  

Figure 66: Programmable interconnects.

Programming FPGAs

Here is a basic programming sequence. There are many variations and options in practice.

1.

Enter the design using a schematic or hardware description language.

2.

Synthesize the design to obtain files suitable for simulation and/or implementation.

3.

Implement the design:

(a)

translation

(b)

technology mapping

(c)

place and route

(d)

timing

(e)

create bitstream file.

4.

Use download software to program the design into the target FPGA device via a cable.

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