D Flip Flop

Create a new Xilinx schematic project called dff-s, download the zip file dff-s.zip and extract the schematic dff-s1.sch into your main project folder dff-s. Open the schematic and add to the project. Start the Logic Simulator.

To configure the clock waveform:

1.: Open the Select Stmulators window from the Logic Simulator.
2.: Click on the Formula... button, to open the Set Formulas tool.
3.: In the Set Formulas tool, double click on the line C1:, and enter the formula 100ns=H 100ns=L, as shown in Figire 35.
4.: Click accept and then close.
5.: Back in the Select Stmulators window, the clock symbol C1 should be red, indicating it is has been configured for use.
6.: Select CLOCK in the waveform viewer and set the stimulus to be C1.

The other inputs can be configured as usual.

**Figure 35:** Set Formulas tool.
$\begin{figure} \begin{center} \epsfig{file=images/dffsim1.eps}\end{center}\end{figure}$

Set the simulation time step to 50ns, and simulate, similar to Figure 36.

**Figure 36:** D flip flop waveform.
$\begin{figure} \begin{center} \epsfig{file=images/dffsim2.eps}\end{center}\end{figure}$

1.: When can the output (and state) change relative to the CLOCK and input D?
2.: Is it synchronous, or asynchronous?
3.: Is it positive or negative edge triggered?
4.: How does this differ from the D latch?

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