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### JFET Biasing

Consider an n-type JFET. It requires VGS to be negative. Perhaps the simplest way to achieve this is via the self-bias   circuit of Figure 132.

The gate is tied to ground (0 V) via a resistor RG (usually large, M), so VG=0 V (recall that due to the high input resistance we assume IG=0). A current ID will flow through RD and RS, so VS will be positive. Thus VGS is negative. Indeed, VS = ID RS, and so

 VGS = VG - VS = -ID RS (120)

This equation as well as the square law

(recall ID=IDS) must be satisfied, so that

 (121)

This is a quadratic equation for IDS. If ID=IDS and VGS are determined, equation (120) is used to determine RS.

The ID-VDS load line is given by

 (122)

(check this!)

A slightly more complicated and useful bias network is the voltage divider bias   of Figure 133.

In this case, since IG=0 the gate voltage is given by

and hence

 VGS = VG - VS = VGG -ID RS . (123)

This equation as well as the square law (110) must be satisfied. The remaining calculations are similar to the self-bias case,

 (124)

In doing these calculations, one can solve the quadratic equation analytically, or use a graphical or computer method.

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