Consider an n-type JFET. It requires VGS to be negative. Perhaps the simplest way to achieve this is via the self-bias circuit of Figure 132.
The gate is tied to ground (0 V) via a resistor RG (usually large,
M), so VG=0 V (recall that due to
the high input resistance we assume IG=0). A current ID will flow through
RD and RS, so VS will be positive. Thus VGS is negative.
VS = ID RS, and so
The ID-VDS load line is given by
A slightly more complicated and useful bias network is the voltage divider bias of Figure 133.
In this case, since IG=0 the gate voltage is given by
In doing these calculations, one can solve the quadratic equation analytically, or use a graphical or computer method.
ANU Engineering - ENGN2211