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Consider an *n*-type JFET. It requires *V*_{GS} to be negative. Perhaps the simplest
way to achieve this is via the *self-bias*
circuit of Figure 132.

The gate is tied to ground (0 V) via a resistor *R*_{G} (usually large,
M), so *V*_{G}=0 V (recall that due to
the high input resistance we assume *I*_{G}=0). A current *I*_{D} will flow through
*R*_{D} and *R*_{S}, so *V*_{S} will be positive. Thus *V*_{GS} is negative.
Indeed,
*V*_{S} = *I*_{D} *R*_{S}, and so

This equation as well as the square law

(recall

This is a

The *I*_{D}-*V*_{DS} load line is given by

(check this!)

A slightly more complicated and useful bias network is
the *voltage divider bias*
of Figure 133.

In this case, since *I*_{G}=0 the gate voltage is given by

and hence

This equation as well as the square law (110) must be satisfied. The remaining calculations are similar to the self-bias case,

In doing these calculations, one can solve the quadratic equation analytically, or use a graphical or computer method.

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