next up previous contents index

[ENGN2211 Home]

JFET Biasing

Consider an n-type JFET. It requires VGS to be negative. Perhaps the simplest way to achieve this is via the self-bias   circuit of Figure 132.

Figure 132: n-channel JFET self bias.

The gate is tied to ground (0 V) via a resistor RG (usually large, $\approx$ M$\Omega$), so VG=0 V (recall that due to the high input resistance we assume IG=0). A current ID will flow through RD and RS, so VS will be positive. Thus VGS is negative. Indeed, VS = ID RS, and so

VGS = VG - VS = -ID RS (120)

This equation as well as the square law

\begin{displaymath}% latex2html id marker 927
I_{DS} = I_{DSS}(1- \frac{V_{GS}}{V_p} )^2

(recall ID=IDS) must be satisfied, so that

 \begin{displaymath}I_{DS} = I_{DSS}(1 + \frac{I_{DS}R_S}{V_P})^2 .
\end{displaymath} (121)

This is a quadratic equation for IDS. If ID=IDS and VGS are determined, equation (120) is used to determine RS.

The ID-VDS load line is given by

 \begin{displaymath}I_D = \frac{V_{DD} - V_{DS}}{R_D + R_S}
\end{displaymath} (122)

(check this!)

A slightly more complicated and useful bias network is the voltage divider bias   of Figure 133.

Figure 133: n-channel JFET voltage divider bias.

In this case, since IG=0 the gate voltage is given by

\begin{displaymath}V_G = V_{GG} = \frac{R_{G2}}{R_{G1} + R_{G2}} V_{DD}

and hence

VGS = VG - VS = VGG -ID RS . (123)

This equation as well as the square law (110) must be satisfied. The remaining calculations are similar to the self-bias case,

 \begin{displaymath}I_{DS} = I_{DSS}(1 - \frac{V_{GG}}{V_P} + \frac{I_{DS}R_S}{V_P})^2 .
\end{displaymath} (124)

In doing these calculations, one can solve the quadratic equation analytically, or use a graphical or computer method.

next up previous contents index

[ENGN2211 Home]

ANU Engineering - ENGN2211