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Using VHDL for State Machine Design

In this chapter we have looked at methods for designing sequential state machines by hand, as well as some practical issues. These methods will help gives us at least some appreciation of what the VHDL compilers do in taking a VHDL source file and producing an implementation, and certainly we now have the ability to contruct state machines using TTL components.

The general approach is to code the design using the programming style used in Wakerly and by the Xilinx software, as discussed earlier. This style is closely related to the next state/output tables, and is used in many examples. The Xilinx state machine editor is very useful for this approach. However, you should know how to do it by hand.


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