Pedestrian Crossing Controller

As a first example of a synchronous sequential state machine, we look at a simplified pedestrian crossing traffic light controller. This example is studied in detail in the lecture notes; please refer to your notes for full information.

The traffic lights are controlled by a synchronous state machine, with state diagram as shown in Figure 31. The state diagram encodes the operation of the pedx controller.

**Figure 31:** State diagram for the pedestrian crossing traffic light controller.
$\begin{figure} \begin{center} \epsfig{file=images/pedxsd1.eps}\end{center}\end{figure}$

In the state diagram, note:

1.: There are four states, corresponding to four operating conditions, in this case stages in the traffic light sequencing.
2.: In normal operation, the controller is in state s₀, waiting for a request (via the W signal) from a pedestrian to cross the road. In this state, the HALT light is illuminated, as is the GREEN (G) signal for the cars.
3.: Whe the W signal becomes active, the controller moves to state s₁, and the HALT and YELLOW (Y) lights are illuminated.
4.: Then the controller moves through the remaining states corresponding to the familiar traffic light sequence, ultimately stopping in state s₀ waiting for the next pedestrian request.

To help familiarise yourself with its operation, try the simulator: pedx-on-the-web

The design given in the lecture notes yields the circuit of Figure 32.

**Figure 32:** Circuit diagram for the pedx controller.
$\begin{figure} \begin{center} \epsfig{file=images/pedxcct1.eps}\end{center}\end{figure}$

In the circuit diagram, note:

1.: The state is remembered by the pair of flip flops, which serve as memory.
2.: The combinational logic to the left of the flip flops is called the next state logic, and determines the next state value depending on the input value.
3.: Transitions from one state to the next will occur at times specified by the clock; i.e. the state machine of Figure 32 is synchronous.
4.: The combinational logic to the right of the flip flops is called the output logic, and determines the values of the output signals.
5.: The flip flops are of the JK type (see later), and have asynchronous preset, meaning they can be set to store logic 1 on application of a 1 to the P input.

Create a new Xilinx schematic project called pedx-s, download the zip file pedx-s.zip and extract the schematic pedx-s1.sch and simulation state file pedx-s.des into your main project folder pdex-s. Open the schematic and add to the project. Start the Logic Simulator, and load the simulation state pedx-s.des.

Simulate the state machine using the Logic Simulator, and obtain the waveform similar to Figure 33.

**Figure 33:** Simulation waveform for the pedx controller.
$\begin{figure} \begin{center} \epsfig{file=images/pedxswav1.eps}\end{center}\end{figure}$

Answer the following questions concerning your simulation, and sketch in your notebooks:

1.: Identify the CLOCK signal, the inputs, outputs and states.
2.: How do the states and outputs change relative to the CLOCK? At what point in the clock cycle? How is this related to the input values?
3.: By observing the state variables AB, determine what state the machine is in at each time. Relate this to the state diagram.
4.: What happens when RESET is activated? When does any transition occur relative to the CLOCK?

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