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Synthesis

If you look at the main Project Manager window, you will notice that the design flow is a bit different, Figure 28.


  
Figure 28: Xilinx VHDL design flow.
\begin{figure}
\begin{center}
\epsfig{file=images/andor-v5.eps}\end{center}\end{figure}

The VHDL source code must first be synthesized; i.e. a gate-level version of the circuit is created for simulation and implementation.

Click on the synthesize icon and make selections as follows, Figure 29:


  
Figure 29: Synthesis selections for andor.
\begin{figure}
\begin{center}
\epsfig{file=images/andor-v6.eps}\end{center}\end{figure}

When the synthesis operation has successfully completed, the synthesis icon should be checked.


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