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Synthesis

The VHDL source code must now be synthesized; i.e. a gate-level version of the circuit is created for simulation and implementation.

Click on the synthesize icon and make selections as follows, Figure 30:

• the top level should always indicate the top-level VHDL entity, in this case adder4
• target family is XC4003E
• device is 4003EPC84
• click RUN

  

Figure 30: Synthesis selections for adder4-v.

When the synthesis operation has successfully completed, the synthesis icon should be checked.

Note: We have not specified external pin connections. This could be done by creating the .ucf file as usual.

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