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Create a Macro Symbol from a VHDL Source File

1.

Download the following file and save in your main adder4vs directory: adder-v.vhd.

2.

Open the file adder-v.vhd using the HDL Editor, and view the VHDL code.

3.

Edit the file, inserting your name and student number. ( All of your source files should show your name and student number.)

4.

Check the VHDL syntax:

Synthesis $\to$ Check Syntax

5.

Create the macro symbol adder-v from the VHDL code:

Project $\to$ Create Macro

Note: In general, if you were creating a design from scratch, you would want to make sure that the VHDL code was correct before creating a macro symbol. This can be done via simulation, though we won't do so at the moment (do this later if you wish). Also, if you need to edit and change the VHDL code after the macro symbol has been created you will need to update it via Project $\to$ Update Macro

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