Load the PSPICE file jfet-amp1.sch, Figure 47. Your task is to a design value of RD for the best compromise between good gain and output voltage swing.
Exercise:
You may use your curves from the DC bias exercise above, section 8.4.
Draw the load line on the characteristic graph (ID vs VDS) for your value of RS. Plot the DC operating point Q on this load line.
Check for consistency with the DC bias exercise above, section 8.4.
Lecture Notes : FET Transistor Circuits : Small Signal Amplifiers
To measure the gain, measure the peak-to-peak values of vs and vout and calculate the ratio vout/vs.
ANU Engineering - ENGN2211