[ENGN2211 Home]

   
DC Bias

Load the PSPICE file jfet-dc3.sch, Figure 45.

  

Figure 45: Circuit for JFET DC operating point (self bias).

Exercise:

1.

Examine the self bias circuit of Figure 45 and calculate V_G, V_GS, I_D and V_DS and V_D using the relations

V_GS = -I_D R_S ,

$$I_D = \frac{V_{DD}-V_{DS}}{R_D +R_S} ,$$

$$I_D = I_{DSS}( 1- \frac{V_{GS}}{V_p} )^2 .$$

(Use R_D=1 k$\Omega$, R_S=500 $\Omega$, and the values of I_DSS and V_p you determined above.)

2.

Simulate the circuit for the given setup. Is the transistor J₁ in the active region? Why?

3.

We now wish to investigate the effect of varying the source resistor R_S on the DC operating point, and in particular on I_D and V_DS. We do this using DC sweep, with R_S set up as a parameter, varying between 100 $\Omega$ and 10 k$\Omega$.

Enable DC sweep and simulate again. Obtain plots of I_D and V_DS=V_D-V_S vs R_S (similar to Figure 46).

4.

Explain what you see.

Note carefully the effect of R_S on I_D and V_DS.

5.

Draw load lines on the characteristic graphs (I_D vs V_DS) for three values of R_S: 0.1, 0.5 and 1.0 k$\Omega$.

The horizontal intercept is V_CC=10 V, and the vertical intercepts are given by

$$I_{D(max)} = \frac{V_{DD}}{R_D+R_S}$$

Plot the operating point Q corresponding to item 1 (on the R_S=0.5 k$\Omega$ load line).

These results can be used for the amplifier of the next section.

  

Figure 46: DC operating point varies with R_S.

[ENGN2211 Home]