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Structure of a VHDL File

Every VHDL source file must have an entity-architecture pair, and may have additional modules, each with their own entity-architecture pairs, Figure 49.

  

Figure 49: VHDL file structure.

  Entity declarations include a list of interface signals that can be used for connection to other modules or external signals declared using the port statement:

entity entity-name is
         port( [signal declarations] );
end entity-name;

  Architecture declarations specify the functionality of the digital system:

architecture architecture-name of entity-name is
         [declarations];
begin
         [architecture body];
end architecture-name;

Notes:

• All VHDL statements must end with a semicolon (;).

• VHDL is generally not case sensitive.

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