next up previous contents index

[ENGN3213 Home]

Signals, Variables and Constants

We think of ports in the entity declarations as specifying input/output signals. Signals are used in signal assignment statements, such as  

X <= (A and B) or C

  Variables are used for local storage inside processes (see below), and are assigned values in variable assignment statements, such as

Y := X xor Z;

  VHDL also supports the use of constants; see the examples in the labs/tutorials, and in Wakerly.

ANU Engineering - ENGN3213