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Introductory BJT Circuits

Consider again the circuit of Figure 96. We first do a DC analysis using the DC model of Section 8.2.3. You can either re-draw the circuit substituting the model of Figure 100 for the transistor, or simply keep the same diagram and write explicitly the algebraic equations

$$V_{BE} = 0.7 \ V, \ \ \ I_C = \beta I_B, \ \ \ I_E = I_B + I_C$$ (93)

corresponding to the DC model.

The left part of the circuit gives, using KVL,

V_BB = I_B R_B + V_BE

and hence the base current is given by

$$I_B = \frac{V_{BB} - 0.7 \ V}{R_B} .$$ (94)

If V_BB is given, this can be solved to get I_B. The right part of the circuit gives

V_CC = I_C R_C + V_CE

This gives a linear relationship (load line)  for I_C and V_CE:

$$I_C = \frac{V_{CC} - V_{CE}}{R_C}$$ (95)

Since this must equal $\beta I_B$, one can solve for V_CE to find the quiescent or operating point Q.     This is often done graphically, as shown in Figure 103.

  

Figure 103: DC load line for the circuit of Figure 96.

The operating point Q can be anywhere on the load line that is intersected by a collector characteristic. Note that this is the same as the diode method where one uses device characteristics in combination with circuit equations.

Importantly, V_CE determination allows one to verify if the initial assumption of active bias is correct!

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