Description

Think for a moment about how you learned to add and subtract in primary school:

$\begin{displaymath}\begin{array}{cccc} & 1 & 9 & 0 \\ + & 3 & 3 & 1 \\ \hline ... ...3 & 3 & 5 \\ - &1 & 5 & 3 \\ \hline & 1 & 8 & 2 \end{array}\end{displaymath}$

In the addition, the middle (10's) column sum results in 12, which is 2 with a carry out of 1; this becomes a carry in of 1 in the 100's column that is added to the sum in that column. In the subtraction, the middle difference requires a borrow from the 100's column, which becomes a borrow out from the 10's column and a borrow in for the 100's column; in the 100's column the borrow in is also subtracted to produce the correct answer. Note that the calculations proceed from right to left, and information ripples to the left as the calculation proceeds.

We can do the same in binary - the method is exactly the same, the base is different. Here are some examples:

$\begin{displaymath}\begin{array}{ccccc} & 1 & 1 & 0 & 0 \\ + & 1 & 1 & 1 & 0 \\... ... \\ - & 0 & 1 & 1 & 0 \\ \hline & 0 & 1 & 1 & 0 \end{array}\end{displaymath}$

Consider the addition and the sum in the 100's column, 1+1=10; the carry out is 1 which becomes a carry in for the 1000's column, where the carry in is added to the sum: 1+1+1=11; this sum produces a cary out of 1 to the 10000's column. Now consider the subtraction. The 10's column produces a borrow out of 1 which becomes a borrow in of 1 to the 100's column; this must also be subtracted so we have 1-1-1 which requires a borrow to give 11-1-1=1 (3-2=1) creating a borrow out of 1 from the 100's column. (Note that in many digital systems arithmetic is implemented using 2's complement representation of positive and negative numbers, though we won't do this here.)

These arithmetic algorithms are determined by specifying what happens to sums and differences in columns - in the binary case this is called a bit slice architecture. In this lab your will design combinational circuits to implement 1-bit binary addition and subtraction. The resulting bit-slice design could in principle be used for multibit binary addition and subtraction by interconnecting 1-bit units. Figure 62 shows a 4-bit binary adder with a bit-slice architecture: A₃A₂A₁A₀ + B₃B₂B₁B₀ = S₃S₂S₁S₀.

**Figure 62:** Bit slice 4-bit adder.
$\begin{figure} \begin{center} \epsfig{file=images/hlab8img1a.eps}\end{center}\end{figure}$

Figure 63 shows the block diagram of the circuit you are to design.

**Figure 63:** Arithmetic circuit block diagram.
$\begin{figure} \begin{center} \epsfig{file=images/hlab8img1.eps}\end{center}\end{figure}$

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