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Small Signal Amplifier

Load the PSPICE file jfet-amp1.sch, Figure 47. Your task is to a design value of R_D for the best compromise between good gain and output voltage swing.

  

Figure 47: Small signal JFET amplifier.

Exercise:

1.

Choose a (standard) value of R_S so that the DC operating point is such that $I_D \approx I_{DSS}/2$ (approx.). Set in PSPICE.

You may use your curves from the DC bias exercise above, section 8.4.

2.

Simulate and check the DC bias is correct.

Draw the load line on the characteristic graph (I_D vs V_DS) for your value of R_S. Plot the DC operating point Q on this load line.

Check for consistency with the DC bias exercise above, section 8.4.

3.

Calculate the gains A_in,out and A_s,out.

Lecture Notes : FET Transistor Circuits : Small Signal Amplifiers

4.

Enable transient analysis and simulate. Determine from your simulations results the AC gain A_s,out. Compare with theory.

To measure the gain, measure the peak-to-peak values of v_s and v_out and calculate the ratio v_out/v_s.

5.

Experiment with different values of v_S, R_So and R_L and note the effects. Discuss.

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