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A Simple One-Way Serial Channel

Figure 55 describes a simple one-way serial channel. Here, an assembly or C program configures the UART 1 module of the 5206 microprocessor chip as a serial transmitter, while VHDL code implements a serial receiver in the 4003E FPGA chip. Here is some sample code you can download and use:

• txs.s - transmits a byte
• rx.vhd - receives a byte

Assemble and download the transmitter code to the SBC. This code will transmit at 1200 baud. To transmit a byte, enter it into register D7 before running the code:

rm d7 34
go 10000

Create a Xilinx project rx for the serial receiver and synthesize and implement. The Xilinx pins should be set up as follows:

signal	Xilinx pin	I/O no.	ribbon cable no.	LED /SW
RDR<7>	P84	8	30	D1
RDR<6>	P3	7	31	C1
RDR<5>	P4	6	32	B1
RDR<4>	P5	5	33	A1
RDR<3>	P6	4	34	D0
RDR<2>	P7	3	35	C0
RDR<1>	P8	2	36	B0
RDR<0>	P9	1	37	A0
RxD	P10	0	38	-
CLK	P13	-	40	-
RST	P19	-	-	SW3-1
READY	P61	-	-	d1
SAMPLE	P77	15	23	-

The basic procedure for setting up the serial link is as follows:

• Establish a row of pins on the breadboard for a GROUND rail - connect to the digital trainer board ground.

• Connect the SBC cable ground pin to the GROUND rail.

• Connect the FPGA ribbon cable ground to the GROUND rail.

• Connect the SBC cable txd1 pin to the FPGA ribbon cable pin 38 (I/O0).

• Connect the FPGA ribbon cable pin 40 to the digital trainer board TTL clock.

• Set the clock frequency to $16 \times 1,200 = 19,200$ Hz (you will need to use the CRO to get the correct frequency - see below).

• Connect the 8 RDR bits available on the FPGA ribbon cable to the two 7-segment displays on the digital trainer board.

Once the receiver has been downloaded to the FPGA and the set-up is complete, test the link by sending some data. The data in the low-order byte of D7 should appear in the 7-segment display.

The receiver uses a clock signal of frequency $16 \times 1,200 = 19,200$ Hz, 16 times the baud rate. Its operation is shown in Figure 58.

  

Figure 58: Receiver detection of byte $34.

The receiver detects the stop bit by looking at RxD checking for 0 for eight consecutive clock cycles, which brings it to the middle of the stop bit period. The receiver waits for 16 clock cycles and then samples the first data bit in the middle of its period. This process repeats for all data bits, and terminates when the whole byte has been received. Counters are used to implement the delay and count operations.

You may wish to simulate the receiver to help understand its operation. In particular, it is suggested you draw block and state diagrams.

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