[ENGN3213 Home]

Specification

a.

The basic operation is specified in the following table:

RS (run/stop)	MODE	Operation
0	$\phi$	HOLD
1	0	binary count
		0,1,2,3,4,5,6,7,0,...
1	1	Gray count
		0,1,3,2,6,7,5,4,0,...

b.

The outputs are specified as follows:

output	function	display device
LED[2:0]	binary code for current count value	7-segment display
Y=0	odd count value	LED
Y=1	even count value	``

c.

The Xilinx and digital trainer board resources and pin connections are as follows:

	Xilinx	Xilinx board	Trainer board
signal	pin	resource	resource
MODE	P19	SW3-1	-
RS	P20	SW3-2	-
Y	P60	LED-1	-
CLOCK	P13	-	TTL clock
LED<0>	P10	-	7-seg A
LED<1>	P9	-	7-seg B
LED<2>	P8	-	7-seg C

d.

The counter is to be a synchronous sequential FSM which changes state on an active CLOCK edge. The CLOCK input is connected to Xilinx pin P13.

e.

The RESET input should set the current count to 0 when activated.

f.

A partial state diagram for the binary/gray counter is shown in Figure 50. There are eight (8) states, only 4 of which are shown in the figure. You will need to complete the state diagram according to the specifications.

  

Figure 50: Binary/Gray Counter partial state diagram.

[ENGN3213 Home]