Description

You are to design, implement and test on the Xilinx FPGA a 3-Bit Binary/Gray Counter, as shown in Figure 49.

**Figure 49:** Binary/Gray Counter Block Diagram.
$\begin{figure} \begin{center} \epsfig{file=images/bingray1.eps}\end{center}\end{figure}$

The counter counts up in the usual binary sequence when MODE=0, and in the Gray sequence when MODE=1. The count is output to a 7-segment display, and the output Y indicates whether the current count is odd or even. RESET, CLOCK and RS (run/stop) inputs are used.

ANU Engineering - ENGN3213