Up/Down/Stop Counter

Exercise. Use the State Editor to create VHDL code for the up/down/stop counter (see lecture notes, Chapter 4). Synthesize, simulate, and implement. The inputs and outputs are shown in Figure 40, where the output cnt[1:0] is a vector, and a fragment of the state diagram is shown in Figure 41.

**Figure 40:** State diagram fragment for the up/down/stop counter in the `State Editor`.
$\begin{figure} \begin{center} \epsfig{file=images/udstate2.eps}\end{center}\end{figure}$

**Figure 41:** State diagram fragment for the up/down/stop counter in the `State Editor`.
$\begin{figure} \begin{center} \epsfig{file=images/udstate1.eps}\end{center}\end{figure}$

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