In this lab you are to implement the reaction timer of HLAB 5 in software on the SBC, making use of appropriate hardware resources on the Xilinx Demo Board and Digital Trainer Board. The SBC is to implement the main functionality, and use a one-way serial communication channel to transmit the reaction times to a pair of 7-segment displays; the Xilinx FPGA being used as a serial receiver. In this way you will create a software/hardware system making use of assembly and/or C program modules for the SBC and VHDL hardware modules for the FPGA.
You will have two 2-hour lab sessions available for this assignment. Because of the complexity of the task, it is suggested that you break it up into smaller parts, develop and test each part, and then combine.
Additional details and code are provided in the Appendix 17.8.
ANU Engineering - ENGN3213