The basic steps in the design process are as follows. Your design must be complete and fully documented as part of the PREPARATION.
It is suggested you use the state editor to produce VHDL code for the controller, and you can use a cascade of four synchronous decade counters to create a schematic for your timer module.A decade counter such as Xilinx schematic part CD4LE can be used in the design of the timer module.
ANU Engineering - ENGN3213