Read through these notes thoroughly, and do any additional reading from the textbook and lecture notes to help your understanding.
Complete the simulation of the up/down/stop counter from CLAB3. Have the schematic project ready to implement and test in the hardware lab.
Complete the state diagram/VHDL design and software simulation of the binary/gray counter. Include design details in your notebooks and paste in state diagram, VHDL code, and simulation printouts.
Keep the project and files in your computer account so they can be accessed and used in the lab.
Reading: Wakerly, section 8.4, especially 8.4.2, 8.4.6, and 9.2. Also read Wakerly, section 7.3.
ANU Engineering - ENGN3213