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Structural VHDL

A structural VHDL model for the pedestrian crossing controller discussed in lectures is given in the file pedxv1.vhd:

-- ENGN3213, pedxv1.vhd
-- Name: MRJ, 24/11/00
-- structural implementation of PEDX controller


library ieee;
use ieee.std_logic_1164.all;

entity	pedx is
	port(w, reset, clock : in std_logic;  
		green, yellow, red, halt : out std_logic;
		walk : inout std_logic);
end pedx;

architecture pedx_arch of pedx is   
component jkffv is 
  port (CLOCK: in STD_LOGIC;
        J: in STD_LOGIC;
        K: in STD_LOGIC;
        P: in STD_LOGIC;
        Q: inout STD_LOGIC;
        QN: inout STD_LOGIC);
end component;
signal  ja, ka, jb, kb, a, an, b, bn  : std_logic;

begin   
	ja <= b;
	ka <= b;
	jb <= a or w;
	kb <= '1';
	jka:	jkffv	port map(clock, ja, ka, reset, a, an); 
	jkb:	jkffv	port map(clock, jb, kb, reset, b, bn); 
    green <=  an and bn;
    yellow <=  an and b;
    red <=  a;
    walk <=  a and bn;
    halt <=   not walk;
end pedx_arch;

In this structural VHDL code, the JK flip flop of section 5.4 is used as a component.

1.

Draw a top-level block diagram of the pedx controller from the structural VHDL code showing its inputs and outputs.

2.

Draw a circuit diagram of the pedx controller from the VHDL code showing the JK flip flop components and interconnections, and compare with the schematic diagram from CLAB3.

3.

Create a Xilinx VHDL project pedxv1 for the pedx controller.

4.

Copy the VHDL source code for the JK flip flop jkffv1.vhd from section 5.4 into the top-level project folder jkffv1.

5.

Save the pedx VHDL code pedxv1.vhd into the top-level project folder jkffv1.

6.

Open the two files with the HDL Editor, check the syntax, and add them to the project.

7.

Include your name and student number in the file as a comment.

8.

Synthesize the project using the Synthesis tool. Make sure the top-level entity is pedx.

9.

Simulate the design, and check for correct operation. Include printouts in your notebooks.

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