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Add a VHDL Source File for the Full Adder

1.

Download the following file and save in your main adder4-v directory: adder-v.vhd (same file as above).

2.

Open the file adder-v.vhd using the HDL Editor, and view the VHDL code.

3.

Edit the file, inserting your name and student number. ( All of your source files should show your name and student number.)

4.

Check the VHDL syntax:

Synthesis $\to$ Check Syntax

5.

Add the VHDL source file adder-v.vhd to the project:

Project $\to$ Add to Project

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