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Interrupts and Exceptions

    Interrupts free processors from the task of continually monitoring the status of peripheral devices. When a peripheral requires attention, it requests the processor to interrupt what it is currently doing. Using a system of priorities, the processor may service the interrupt, or leave the request pending (or masked). Peripherals make interrupt requests via interrupt lines, See Figure 114, and may supply an interrupt vector specifying which interrupt service routine to execute.    

Figure 114: Peripherals and interrupt lines.

Interrupt requests are asynchronous, since they can occur at any time. The interrupt service routine is a piece of code similar to a subroutine that performs the required actions. Unlike a subroutine, it is terminated by an RTE instruction, and also the address of the service routine is obtained from the exception vector table (see below).

Figure 115 shows the execution of a main program being interrupted, and an interrupt service routine being executed.

Figure 115: Interrupt servicing.

The basic steps in processing an interrupt are as follows (once the CPU decides to service it):

The current instruction is completed.

The contents of PC and SR are saved on the stack. This preserves the return address and processor status.

The machine jumps to the interrupt service routine, and begins execution of it. (The address of the routine was obtained via the exception vector table.)

One completion of the execution of the interrupt code, the processor status and return address are popped from the stack and restored (this is the purpose of the RTE instruction).

Program execution continues at the return address.

This is organised so that the operation of the interrupted program is unaffected by the interrupt (apart from the delay), so that the interrupt mechanism is transparent.

  The 68000 and 5206 support prioritized interrupts, using seven levels. An interrupt request will not be serviced unless it is at a higher level than the current interrupt or program. Bits I2, I1, I0 of SR constitute the interrupt mask, which specifies the level below which interrupts will not be processed. When an interrupt is serviced, the interrupt mask is set to the level of that interrupt.

Peripherals use the IPL inputs to inform the processor of their level, Figure 116. External hardware is used to generate this 3-bit code, Figure 117.

Figure 116: Interrupt pins (ACTIVE L).

Figure 117: Interrupt interface.

The processor needs to know which interrupting device is requesting service, and a system of vectoring is used. A vector is a pointer to an interrupt service routine, so the interrupting device needs to specify its interrupt vector number to the CPU via the data bus, during the interrupt acknowledge cycle (IAQK).  

  This is simplified somewhat in the case of autovectored interrupts, where the CPU generates the vector number. In the case of the 68000, the VPA pin is asserted (active low) to indicate an autovectored interrupt. E.g., if IRQ2 and VPA are asserted, the autovector 0x1A = 26 is generated. If there is more than one autovectored device with the same interrupt level, the service routine must poll the devices to determine which needs servicing. For the 5206, bit AVEC in one of the ICR registers is used to indicate whether the interrupt is autovectored or not.

  The exception vector table in abbreviated form is as follows:

vector no. vector address (HEX) exception type
0 000 RESET - initial value of SSP
- 004 RESET - initial value of PC
2 008 bus error
3 00C address error
4 010 illegal instruction
5 014 divide by zero
6 018 CHK instruction
8 020 priviledge violation
9 024 trace
25 064 Level 1 autovector
26 068 Level 2 autovector
27 06C Level 3 autovector
28 070 Level 4 autovector
29 074 Level 5 autovector
30 078 Level 6 autovector
31 07C Level 7 autovector
32 080 TRAP # 0
33 084 TRAP #1
64 100 user interrupt vector
65 104 user interrupt vector
255 3FC user interrupt vector

The vector address is a longword, stored at memory location 4 times the vector number. So the level 2 autovector uses memory location $4 \times 0x1A = 0x068$ for the address of its service routine.

Note that an interrupt is a type of exception, an exception being a condition that needs special attention such as RESET, divide by zero, error conditions, and so on. The exception table specifies addresses of routines for dealing with them.

Exceptions and interrupts are discussed at some length in Clements, Chapter 6.

Detailed documentation is provided in Section 6 of the Motorola M68000 User Manual, and in Section 7 of the Motorola MCF5206 User Manual.

The assembly language program irq1as.s in HLAB6 shows how to set up and use the 5206's external interrupt IRQ1. The three IPL/IRQ pins on the 5206 can be configured as IPL inputs as discussed above (similar to the 68000), but they can also be configured for three direct external interrupts, specifically IRQ1, IRQ4 and IRQ7. In the SBC5206 microcomputer, IRQ7 is connected to the black abort button (IRQ7 is the highest level), IRQ4 is used by a device on the circuit board (the HC901), and IRQ1 is available to the user. Other 5206 modules, such as the timers and UARTs, can request interrupts (see section 7.3.1 of the user manual). The 5206 uses four priorities for each interrupt level, so each device must have a unique level and priority.

IRQ1 is configured by the dBug monitor as a level 1, priority 1, autovectored interrupt. The control register ICR1 is set to 0b10000101 (see section of the 5206 user manual). The AVEC bit is the MSB of ICR1, and it is set to 1 to indicate autovector. There is no IACK cycle for such autovectored interrupts.

The main routine of irq1as.s places the address of irq1-handler, the interrupt service routine, at memory location $4 \times 25 =100$ = 0x64 as part of the set up for the use of IRQ1.

The interrupt mask register IMR is used to enable or disable interrupts. When a bit in IMR is set, the associated interrupt is masked, i.e. disabled. Bit 1 of IMR corresponds to IRQ1. To enable IRQ1, the main routine in irq1as.s sets IMR=0x3F7C (which clears bit 1). To disable IRQ1, the interrupt service routine irq1-handler sets IMR=0x3F7E (which sets bit 1). (Bit 7 is left cleared to keep the abort button operational, i.e. IRQ7 is unmasked.)

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