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JK Flip Flop

We have seen that flip flops are often used as memory in the design of state machines. However, flip flops are themselves state machines. The state diagram for a JK flip flop is shown in Figure 37. Compare with the JK flip flop operation and transition tables.

  

Figure 37: JK flip flop state diagram.

We now build a JK flip flop in VHDL. To do this, we use the Xilinx State Editor, which creates VHDL from a state diagram.

Create a new Xilinx VHDL project called jkffv1, download the zip file jkffv1.zip and extract the state diagram file jkffv1.asf into your main project folder jkffs1.

1.

Start the State Editor from the Design Entry icon in the main Project Manager window.

2.

Select Create Empty, then OK.

3.

In the State Editor, open the state diagram file jkffv1.asf, Figure 38.

Note:

(a)

Inputs and outputs are listed at the top.

(b)

VHDL syntax is used to specify transitions. (Compound expressions should be enclosed in parantheses, since they will form part of if statements.)

(c)

Outputs are also specified using VHDL syntax, though with multiple outputs separated by semi-colons.

(d)

Two outputs are specified, Q and $QN = \overline{Q}$.

(e)

The preset input P when activated sets the machine to state S₂ (Q=1), using the RESET symbol.

4.

Create VHDL code via:

Synthesis $\to$ HDL Code Generation

Click NO to viewing code when complete.

5.

Start the HDL Editor from the Design Entry icon in the main Project Manager window.

6.

Select Create Empty, then OK.

7.

In the HDL Editor, open the VHDL file jkffv1.vhd that was just created by the State Editor.

8.

Check the syntax. (The VHDL code generation software can't check or fix wrong VHDL code in state diagrams.)

9.

Add the VHDL file jkffv1.vhd to the project jkffv1.

10.

Examine the VHDL code, and note the use of the process for determining the next state, the way it is set up to respond to the clock, and also notice the output logic. Compare with the style discussed in Wakerly, section 9.2.

11.

Include your name and student number in the file as a comment.

12.

Synthesize the project using the Synthesis tool. Make sure the top-level entity is jkffv.

13.

Using the Logic Simulator, simulate the behavior of the JK flip flop, and check against the state diagram specification.

14.

Finally, implement the design using the Implementation tool.

  

Figure 38: State Editor - JK flip flop.

This example illustrates the method we will use to create VHDL state machine designs.

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