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Decoders and Encoders

A decoder   is an n-input 2n output device which activates one and only one of its outputs depending on the unique input pattern, Figure 174.


  
Figure 174: Decoder.
\begin{figure}
\begin{center}
\epsfig{file=images/msiimg1.eps}\end{center}\end{figure}

$Y_i=m_i \cdot EN$, where mi is the ith minterm (out of 2n total outputs). Y is active L. 
EN is ENABLE (active L).
$A_1,\ldots,A_n$ are n inputs

When EN is active, one and only one Yi is active; all other outputs are inactive.

When EN is inactive, all outputs are inactive.

Example. Consider the 2-4 (n=2) decoder specified in the truth table:

EN A1 A0 Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

The output functions are given by

\begin{displaymath}\begin{array}{rl}
Y_0 & = \overline{A}_1 \overline{A}_0 EN \\...
... {A}_1 \overline{A}_0 EN \\
Y_3 & = {A}_1 {A}_0 EN
\end{array}\end{displaymath}

A circuit implementation is shown in Figure 175.


  
Figure 175: Decoder circuit (n=2).
\begin{figure}
\begin{center}
\epsfig{file=images/msiimg2.eps}\end{center}\end{figure}

Example. Decoders can be used to implement combinational logic functions. Consider the cannonical SOP expression

\begin{displaymath}F(A,B,C) = \sum m(1,3,4,7) .
\end{displaymath}

A 3-8 decoder circuit implementing this function is shown in Figure 176.


  
Figure: Decoder (n=3) used to implement the logic function $F =\sum m(1,3,4,7)$.
\begin{figure}
\begin{center}
\epsfig{file=images/msiimg3.eps}\end{center}\end{figure}

Encoders   perform the function opposite to that of decoders. Encoders have up to 2n inputs and n outputs, and generate an n-bit word for each of the inputs.

In priority encoders,   any number of the inputs can be active, so a priority scheme selects a particular input line.

An n-m encoder block is shown in Figure 177.


  
Figure 177: Encoder.
\begin{figure}
\begin{center}
\epsfig{file=images/msiimg4.eps}\end{center}\end{figure}

Here, $m \leq 2^n$, EI denotes input enable, OE denotes output enable, which together with GS is used for cascading.

A truth table indicating how the priority scheme is implemented is:

EI I2 I1 I0 GS Y1 Y0 EO
0 X X X 0 0 0 0
1 1 X X 1 1 1 0
1 0 1 X 1 1 0 0
1 0 0 1 1 0 1 0
1 0 0 0 0 0 0 1

I2 has the highest priority, with code 11; second is I1, with code 10; and lowest is I0, with code 01. When the device is inactive, the code is 00.


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