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Design Flow: Entry, Simulation and Implementation

VHDL is used for a range of purposes, including:

• simulation
• synthesis

Simulation can be done at different levels, such as

• Ideal: the ideal behaviour not taking into account any physical limitations

• Physical: physical limitations such as propagation delays may be modelled to varying degrees.

• Target specific: detailed modelling of the target technology

Synthesis refers to the procedure for creating the desired physical implementation of a design, and is part of the design flow. The design flow may involve several levels of simulation, and iteration.

For our purposes in this course the basic design flow will be:

1.

Schematic and/or VHDL design entry

2.

ideal or part-physical simulation

3.

synthesis

The Xilinx Foundation software tools will be used for design entry, simulation and synthesis.

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