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Up/Down/Stop Counter

Implement and test using Xilinx 4003EPC84 FPGA hardware the up/down/stop counter you simulated in CLAB3. The Xilinx and digital trainer board resources and pin connections are as follows:

	Xilinx	Xilinx board	Trainer board
signal	pin	resource	resource
ud (M)	P19	SW3-1	-
stop (S)	P20	SW3-2	-
clock	P13	-	TTL clock
Y	P61	LED-1
cnt<0> (B)	P10	-	7-seg A
cnt<1> (A)	P9	-	7-seg B

1.

Create a UCF using the information in this table. Synthesize and implement your design.

2.

Wire up the connections between the 7-segment displays (active high, decoded) on the trainer board and the ribbon cable connection to the Xilinx board.

3.

Make sure earth connections are made between the cable and the trainer board ground.

4.

The CLOCK for a sequential design must ALWAYS be connected to Xilinx pin P13 (ribbon cable pin 40).

5.

Set the trainer board clock at a slow speed and observe it on the CRO.

6.

Test the circuit by using the switches and watching the LEDs and 7-segment display.

7.

Document your implementation and testing with tables, graphs, waveform sketches, etc.

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