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Binary/Gray Counter

Implement and test the binary/gray counter you designed using Xilinx 4003EPC84 FPGA hardware.

1.

Wire up the connections between the 7-segment displays (active high, decoded) on the trainer board and the ribbon cable connection to the Xilinx board.

2.

Make sure earth connections are made between the cable and the trainer board ground.

3.

The CLOCK for a sequential design must ALWAYS be connected to Xilinx pin P13 (ribbon cable pin 40).

4.

Set the trainer board clock at a slow speed and observe it on the CRO.

5.

Create a suitable UCF file and go through the process of synthesing, implementing and programming using the above pin specs.

6.

Test the circuit by using the switches and watching the LEDs and 7-segment display.

7.

Document your implementation and testing with tables, graphs, waveform sketches, etc.

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