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Creating a New VHDL Source File

Next, open the HDL editor and select use HDL wizard, and click OK. Then use the wizard to create a skeleton file for a VHDL circuit with three inputs (A, B, C), and one output (X):

• select VHDL
• enter a name
• enter the 3 inputs and 1 output, Figure 26.

• click Finish

  

Figure 25: HDL Editor Wizard.

  

Figure 26: VHDL module inputs and outputs.

The following VHDL code skeleton should now appear in your HDL editor window:

library IEEE;
use IEEE.std_logic_1164.all;

entity andorv is
    port (
        A: in STD_LOGIC;
        B: in STD_LOGIC;
        C: in STD_LOGIC;
        X: out STD_LOGIC
    );
end andorv;

architecture andorv_arch of andorv is
begin
  -- <<enter your statements here>>
end andorv_arch;

Replace the comment with the VHDL code for X=AB+C as follows:

library IEEE;
use IEEE.std_logic_1164.all;

entity andorv is
    port (
        A: in STD_LOGIC;
        B: in STD_LOGIC;
        C: in STD_LOGIC;
        X: out STD_LOGIC
    );
end andorv;

architecture andorv_arch of andorv is
begin
  X <= (A and B) or C;
end andorv_arch;

Check the syntax:

Synthesis $\to$ Check Syntax

Next, in the HDL editor:

• Save the file.
• add the file to the project:

  Project $\to$ Add to Project

  See Figure 27.

  

Figure 27: VHDL source file in project.

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