As the textbook Wakerly states, VHDL is easy to learn, but hard to master. The moral is: be careful.
In this course you will learn some basic things about VHDL, and how to use it for digital systems design. But we can't cover all aspects in an introductory course.
It is important to understand that the technology for synthesizing from VHDL source code is still under development, and it is possible to write VHDL code that works great for simulation, but can't be synthesized by synthesis tools. VHDL was originally invented for digital circuit description and simulation, while synthesis followed later. The VHDL examples given in this course (and I believe in the textbook) have been tested and can be synthesized. When you write your own VHDL code, use these examples as a guide, and don't be tempted to treat VHDL like an ordinary programming language, for if you do, you will almost certainly have difficulties.
For further comments on VHDL synthesis, see section 4.7.10 (pp297) of Wakerly.
ANU Engineering - ENGN3213