Project: Hardware Support for Garbage Collection

Overview

Garbage collection provides a very important programming abstraction, but has always come with a performance penalty, in terms of total performance, pauses in applications, and in memory consumption. On the other hand, garbage collection is a very simple process comprising mostly of graph traversal. Prior work has shown that large modern processors are grossly underutilized when performing garbage collection, which could just as easily be performed on a far simpler processor since the performance bottleneck is not processor performance but memory bandwidth. Separately, for decades researchers have floated the idea that memory-bound computation could be moved to memory; that modest compute units could be placed within the fabric of the DRAM. Memory-bound applications could then be run directly from within memory, greatly reducing the performance penalty observed when run from a conventional CPU. However, such designs were not realized because they were not seen as commercially viable. More recently, changes in memory fabrication technology have opened the door to processor-in-memory (PIM) technology becoming commercially feasible.

This project is part of a larger collaboration with Ohio State University and Carnegie Mellon University to develop new PIM architectures for garbage collection. A distinctive feature in our approach is that we intend to provide a very general fabric for garbage collection, rather than simply provide a hardware implementation of a single specific algorithm. This generality makes for a much deeper problem but also for potentially much larger impact as a more general solution is more likely to see commercial uptake.

Themes

Garbage collection
Computer Architecture

Requirements

Coding There are many aspects to this large project and a given student’s focus will depend on their interest and expertise. Experince with Verilog and/or Rust will be helpful.
Analysis Students should have a solid grounding in computer architecture.

Project Length

This project is very open-ended and could be undertaken as a single semester undergraduate project, or as the basis of a PhD. However, unless the student has a strong background in FPGA programming and some background in garbage collection, the start-up time for this project is probably too great for a single semester project.

Project Outputs

This project may produce hardware designs, possibly Verilog, and possibly published articles.